Datastreams are transmitted, for example, as AMI (Alternate Mark Inversion) datastreams. In the AMI data transmission method, two lines are provided without DC component for the transmission of datastreams, the analog signals on one line being inverted with respect to the analog signals on the other line.
In the text which follows, logical signals are signals, the signal level of which changes from one logical state to another logical state and the signals can assume a minimum datastream value, a baseline value or a maximum datastream value. In this arrangement, the minimum datastream value is called a logical “−1”, while the value of a baseline is called a logical “0” and the maximum datastream value is a logical “+1”. Between all of these signal values, transitions can take place, i.e. there are 0/1 data transitions, 1/0 data transitions, 0/−1 data transitions, 1/0 data transitions which will be called single-step data transitions in the text which follows. Furthermore, there are −1/1 data transitions and 1/−1 data transitions which will be called double-step data transitions in the text which follows.
The information to be transmitted is digitized in such a manner that digital datastreams are provided with a multiplicity of the abovementioned data transitions. The reception and further processing of digital datastreams require that a reference clock signal can be derived directly from the digital datastream.
Conventionally, a clock signal which is derived directly from detector data transitions, for example from a baseline value to a maximum datastream value or to a minimum datastream value or, respectively, a transition from a minimum datastream value to a maximum datastream value or conversely, is provided as the reference clock signal.
In practice, the direct recovery of a reference clock from the datastream is made more difficult by the fact that the received digital datastreams have jitter i.e. are generally noisy and have “AMI code violations” (bipolar violations).
Conventionally, for example, a time at which a datastream crosses a fixed threshold is taken as the time of a 0/1 data transition.
A disadvantage of this conventional method consists in that bit-pattern-dependent distortion must be avoided, with the consequence that the frequency spectrum of the datastream must also contain frequency components above a center frequency of the useful signal.
This leads to the further disadvantage that noise components are also carried and amplified which can corrupt the useful signal and increase the phase jitter.
FIG. 2 shows a conventional method for determining a reference clock RT from a received digital datastream DS. In a datastream receiver E, a digital datastream DS is received and the received signal is supplied to an edge position detection device F which is supplied with a threshold value from a threshold setting device S. This threshold value can be provided as a positive value or as a negative value and the value is preferably between a minimum datastream value and a maximum datastream value. If the received digital datastreams supplied to the edge position detection device F exceeds or drops below this threshold value, a threshold intersection point between, for example, a 0/1 data transition (or another one of the abovementioned data transition) and the set threshold value is output as the reference clock phase RT.
Furthermore, disturbances such as jitter, i.e. in general noise, band limiting due to the transmission channel etc. have a disadvantageous effect on the determination of a reference clock phase RT which, therefore, has large errors in such a conventional method of determination.
In DE 3442613 A1, a synchronizing stage for obtaining a synchronizing signal is disclosed in which a biternary data sequence referred to a zero line can assume four different amplitude values, namely a maximum positive amplitude value, a maximum negative amplitude value, a positive amplitude value and a negative amplitude value. Although it is possible to obtain with the aid of the arrangement of DE 3442613 A1 a synchronizing signal which is independent of effects of jitter, the circuit arrangement disclosed is extremely complex and costly. Thus, to obtain the synchronizing signal, first, second and third threshold values must be in each case allocated to first, second and third threshold switches or comparators, different threshold switches being addressed depending on the detected edge. The method performed by means of the device of DE 3442613 A1 is extremely complex and is not suitable for reliable and, at the same time, simple recovery of a reference clock from a received digital datastream.